The invention relates to a magnetic memory element and a fabricating method thereof, and more particularly to a magnetic random access memory (MRAM) element having improved switching and switching field offset properties.
A magnetic random access memory (MRAM) is a non-volatile memory which uses multiple layers of magnetoresistive materials as memory storage elements. A typical MRAM array includes a number of conductive bit or digit lines intersected by conductive word lines. At each intersection, a magnetoresistive element, commonly referred to as a magnetic tunnel junction (MTJ) memory element is formed. Each magnetic memory element includes a first pinned ferromagnetic material layer (where the magnetic field is fixed) and a second free ferromagnetic material layer (where the magnetic field can, by programming, assume two different orientations). The two ferromagnetic layers are separated by a non-magnetic layer. The direction of the magnetic vectors in the free and pinned layers, determines the stored state of the magnetic memory element. As such, the magnetic memory element has two stable magnetic states. In one magnetic direction of the free layer, the memory element has a high resistance defined as one logic value, e.g. xe2x80x9c0,xe2x80x9d and in the other magnetic direction of the free layer the memory element has a low resistance, defined as the other logic value, e.g. xe2x80x9c1.xe2x80x9d The stored state of the memory element is generally read by providing a sense current through the magnetic memory element to determine its resistance.
FIG. 1 illustrates an exemplary conventional MRAM structure including three magnetic memory elements 22, having respective associated conductive lines 18, 28 which may serve as word lines and bit lines. Conductive lines 18, typically formed of copper, are formed in an insulating layer 16 formed over under-layers 14 of an integrated circuit (IC) substrate 10. Under-layers 14 may include, for example portions of integrated circuitry, such as CMOS circuitry. A pinned layer 20 is provided over the conductive lines 18. A nonmagnetic layer 24 is provided over the pinned layer 20. The nonmagnetic layer 24 is generally formed of aluminum oxide. A free layer 26 is provided over the nonmagnetic layer 24. Another conductive line 28 is formed over the free layer 26.
Switching of the memory elements 22 are not always reliable. Sometimes, the combined magnetic write fields applied by the word and bit lines might not cause a memory element 22 to switch reliably. This problem is typically solved by increasing crystal anisotropy, coercivity or aspect ratio of the memory elements.
However, increasing the crystal anisotropy, coercivity or aspect ratio leads to another problem: the amount of current for switching the memory elements is also increased. Increasing the amount of current increases the amount of power consumed by the MRAM device and also requires larger bit lines, word lines and write circuits to handle the higher currents. This, in turn, increases the expense of the MRAM device.
A need exists to improve reliability of magnetic memory element switching without increasing the switching current.
The invention provides a magnetic memory element having improved switching and offset, and a manufacturing method thereof. In an exemplary embodiment of the invention, a first conductor in a trench is provided in an insulating layer. An upper surface of the insulating layer and the first conductor are planarized. Then, a pinning structure is formed over the first conductor and the insulating layer. Then, a nonmagnetic layer and a ferromagnetic free layer are consecutively formed over the pinning structure. Next, an antiferromagnetic layer is formed over the ferromagnetic free layer to apply a small bias to the ferromagnetic free layer without causing it to be pinned. The bias allows the ferromagnetic free layer to be centered near the zero magnetic switching field more easily, thus allowing improved repeatability in switching. In a preferred embodiment of the invention, the antiferromagnetic layer is no thicker than about 70 Angstroms. The layers are then patterned into magnetic memory elements.
The above advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
FIG. 1 is a schematic three-dimensional view of a portion of a conventional MRAM structure;
FIG. 2 illustrates a partial cross-sectional view of a semiconductor topography, at an intermediate stage of the processing, wherein a magnetic memory element will be constructed in accordance with the invention;
FIG. 3 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 2;
FIG. 4 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 3;
FIG. 5 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 4;
FIG. 6 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 5;
FIG. 7 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 6;
FIG. 8 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 7;
FIG. 9 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 8;
FIG. 10 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 9;
FIG. 11 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 10;
FIG. 12 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 11;
FIG. 13 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 12;
FIG. 14 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 13;
FIG. 15 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 14;
FIG. 16 illustrates a partial cross-sectional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 15;
FIG. 17 is a partial three-dimensional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 16;
FIG. 18 is a partial three-dimensional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 17;
FIG. 19 is a partial three-dimensional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 18;
FIG. 20 is a partial three-dimensional view of the magnetic memory element at a stage of processing subsequent to that shown in FIG. 19; and
FIG. 21 is a schematic diagram of a processor system incorporating an MRAM constructed in accordance with the invention.